This invention relates to a semiconductor memory device and, more particularly, to a memory device which comprises a sense amplifier circuit used to selectively reinforce the amplification capacity through column select lines which are designated by decoding column address signals.
In recent years, CMOS flip-flop sense amplifier circuits SA11 as shown in FIG. 4 were used as MOS type semiconductor memory devices. Each drain and gate of two N channel transistors are cross coupled and connected to bit line pair BL and BL. Both sources are commonly connected at node SAN by way of the common source line S11. Furthermore, each drain and gate of two P channel transistors for restoring are cross coupled and connected to bit line pair BL and BL. Both sources are commonly connected at node SAP. The bit line pair BL and BL are connected to the data input/output line pair DQ and DQ by way of the DQ gate 41, which is controlled by the column select signal supplied along the column select line CSL.
As shown in FIG. 5, a plurality of sense amplifier circuits SA11 are connected in series to the common source line S11 at the node SAN and connected to the reference voltage potential V.sub.ss terminal through a MOS transistor Qsan for activating the sense amplifier.
In all of the sense amplifier circuits with this type of construction, the transistor current, which lowers the potential of the bit lines to a low level, is discharged at the reference voltage potential terminal V.sub.ss along the source line S11. Here, there is the wiring resistance Rwir along the node SAN and parasitic resistance and capacitance in the activating MOS transistor Qsan.
The number of sense amplifier circuits SA1 tends to increase as the capacitance increases and the total discharge current from the bit lines increases. As a result, the amount of signals read from the input/output line pair DQ and DQ received from the sense amplifier circuits SA11 selected by the column select line CSL tends to reduce causing a decrease in the sense margin. The reason for such a tendency is that all of the columns are amplified by the same condition regardless of selection or non-selection caused by the fact.
In solving this problem, a circuit is proposed as shown in FIGS. 6 and 7, which selectively reinforces the capability of the sense amplifier through the column select line CSL (refer to 1989 Symposium on VSLI Circuits (Digest of Technical Papers)). Connected between the source line S12 of each of the sense amplifier circuits SA12 and the node SAN is normally a type N channel transistor Qn1 used as a resistance element to which the power supply voltage V.sub.cc is applied to the gate. Each source line S12 is connected to the reference voltage potential terminal V.sub.ss by way of the N channel transistor Qn2 which acts as a switching element. A column select signal is applied to the gate of each N channel transistor Qn2 and only transistors in the selected column are made conductive.
When the sense amplifier activating transistor Qsan conducts and the sense operation begins, the transistor current that lowers the potential of the bit lines to a low level is discharged at the reference voltage potential terminal V.sub.ss by way of the transistor Qn1, source line S12 and sense amplifier activating transistor Qsan. Only the transistors Qn2 connected to the selected column sense amplifier circuits SA12 conduct and bypass the sense amplifier circuit and reference voltage potential terminal V.sub.ss. As a result, because only the parasitic capacitance in the selected bit lines is effected, amplification capability is reinforced.
However, due to the transistors Qn1 and Qn2, this kind of construction causes the chip area to be increased. Also, the column select line CSL, which controls the conduction state of the transistors Qn2, must be extended to run through the increased area. In a highly integrated semiconductor memory, when the lengths of both the column select line CSL and the common source node line SAN are increased, the coupling capacitance between the bit lines increases and causes a reduction in the sense margin.
Furthermore, increasing the length of the column select line CSL prevents speeding up the access time.
Still furthermore, because the source lines S12 are selectively connected to the power supply line V.sub.ss by the column select line CSL, each source line S12 must be electrically insulated. This becomes an obstacle in trying to increase integration because the distance between adjacent bit lines is not determined by the size of cell but is determined by the isolation of each of the sense amplifier circuits SA12 with respect to the others.